FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6400 Discussions

How to properly constrain bidirectional I2C SCL / SDA ports ?



We are using an I2C slave controller and like to know how to properly constrain bidirectional SDA and SCL lines to meet setup and hold time requirements.

I searched on the internet and cannot find anywhere advising what constraints to use for I2C SDA, SCL bidirectional ports. Will they be also different constraints for eg START, STOP conditions etc? I will appreciate if you can advise with an example of SDC constraints.

Our I2C interface within the I2C controller module follows the defined behaviour of a I2C slave in the NXP specification (https://www.nxp.com/docs/en/user-guide/UM10204.pdf)

We are using stability check components (checkstable digital filters for the read sda/scl condition to ensure only stable values of SDA and SCL are used by testing over a period of 10 clock cycles (100nS per cycle) that the bit has not changed) for SDA and SCL set to the shortest setting to ensure this works with the 10MHz clock that is used for our FPGA Cyclone V.

We are using a higher frequency clock (10MHz) driving state machine i2c_fsm, bus_strobe  process etc.

The transfer can occur over speed of 100kbits/s in standard mode.

Your prompt reply to this matter will be appreciated.




0 Kudos
1 Reply

Hi Kevin,

May I know if there is any update?

0 Kudos