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Altera_Forum
Honored Contributor I
770 Views

How to "regenerate" an input clock if it's a burst clock

Hi guys, 

 

I have a Cyclone IV E and I have an external board which output a 27 Mhz clock with 8 bit data. The board at the end the chain needs to work another couple of signals (valid and sync) that I generated in VHDL. 

 

Now the solution implemented is not working as expected because the input clock is present only during trasmission of data (188 bytes long). 

 

I need to output a always present clock at 27 Mhz mantain the correct phase between data and other signals (sync & valid) 

 

How could I regenerate the input clock if this is a burst? 

 

I have thought using ALTPLL but I have no idea how to proceed. Any help is very appreciated. 

 

Alex
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7 Replies
Altera_Forum
Honored Contributor I
43 Views

It seems that you are working with TS packets. 

You can use a FIFO with separate clock ports for read & write. 

Use the input 27 MHz clock as write clock and feed the FIFO data port with the same input data. 

Design a simple state machine or a sequential code (process for VHDL OR alway block for Verilog) to read from that FIFO with your local 27 MHz clock which is connected to the read clock port. 

You can now read from FIFO and issue your valid & sync signals based on output of FIFO which is synchronous with your logic.
Altera_Forum
Honored Contributor I
43 Views

Hi Alex, 

 

you need a continous (external) clock for your PLL. This PLL should create the 27MHz on your output. Use the incoming bursted 27MHz directly as clock input to latch the incoming 188byte. 

As the external and internal 27MHz are not phase aligned and may differ slightly in the frequency you need a fifo. RMII Ethernet Phys for example have similar functionality. 

Dirk
Altera_Forum
Honored Contributor I
43 Views

2 minutes too late ...

Altera_Forum
Honored Contributor I
43 Views

Thanks both guys....it's the perfect solution - clean and simple - 

 

@msj: yes I'm playing with Trasport Stream, do you have any experience with? I'm just starting right now
Altera_Forum
Honored Contributor I
43 Views

Apparently not required for the present problem, but it's possible to synchronize a clock over a limited frequency range (e.g. 500 or 1000 ppm) using PLL dynamic phase sift feature and respective user logic. This way you can e.g. implement soft CDR for source synchronous protocols with FPGA that don't have a respective hardware CDR feature.

Altera_Forum
Honored Contributor I
43 Views

Yes, I do. If you have any question, feel free to ask.

Altera_Forum
Honored Contributor I
43 Views

Hi msj, 

 

have you ever worked with scrambled transport stream? I have a CAM and SmartCard and I would be able to receive the transport stream, decrypt it and output to my TS decoder. 

 

Until now I don't find anything useful
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