Dear all,for the parameters in pcie express complier, how to set the values for "number of address pages" and "size of address pages" ? what are the differences if i choose different values? i saw altera manual choose "size of address pages" to be "1 mbyte - 20 bits", while the PCIe wiki example chose "size of address pages" to be "16 mbyte-24 bits".
does the product of "number of address pages" and "size of address pages" need to be a constant (equal to your total bar0 size) ?
Sorry typo error, how to set the values? which one are more reasonable, not "see"--- Quote Start --- Sir you can get help from Google and Youtube to see the values of Number of address pages. --- Quote End ---
Hi binpersonal,I would like to know if you get the answer for the question that you did above. I have a lot of problemas with the configuration of my system using PCIe, and I believe that I have problems with the configurations of "number of pages" and "size of address page". Ii you have the answers, pelase could you share with me? Thanks for helping
An address translation table entry is like a portal from an "block" of local avalon memory space to a "block" of memory the same size in the host.You have to decide how many blocks of memory you need and set that number of table entries. You then have to configure the table entries to do the mapping for you. The lower address bits define the position in the "block", the most significant bits select the table entry, and so the mapping to the appropriate "block" in host memory, and vice versa. That's from memory, but it should point you in the right direction. Nial
Hi GZoinker,According your explanation and the PCIe CORE manual, I have did some configurations on my system and it is working now, but I don't know if I understood how to set this parameters. I will try explain my system and the configurations that I did, and if you could check what I did I will really appreciate. 4 BARS configured - BAR1_0 => 64 bits - BAR2 => 32 bits - BAR3 => 32 bits So I set 4 pages, because I have 4 BARS, is it right? I mapped the addresses of the slaves using the following number of bits (BAR0_1 => 11 bits, BAR2 => 12 bits, BAR3 => 11 bits). So looking the PCIe IP MANUAL, I realized that I could use the the Size of Address Page as 18bits (256kBytes), because: Slave Base Address => 12bits. High => 2 bits (4 Address Page) Low => 18 bits (Size Address Page) In order to have 32 Avalon Address bits. I did this configurations and my system is now working. Is this correct? I'm thinking the right way? Thanks for helping Filipe