FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

IP Core Altera ALTPLL

Altera_Forum
Honored Contributor II
788 Views

I have a problem with the IP Core ALTPLL. I created the IP Core and I gave input to a PLL clock of 48 MHz to obtain an output clock of 96 MHz. When I simulate the output of the PLL I get that for the first six clock cycles at 48 MHz to 96 MHz output consists of xxxx. As you can eliminate this delay of six clock cycles and the x output?

0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
83 Views

I don't think you can remove those. This simulates the fact that the pll needs time to lock on the input clock before the output is valid. The pll has a "locked" output, and you should keep your design in reset as long as the "locked" signal isn't 1. When the pll locks, the locked signal is asserted and the output clock is valid.

Altera_Forum
Honored Contributor II
83 Views

thanks for the reply

Reply