On a custom Stratix IV board, I have two independent DDR3 banks, A and B.
Bank A works fine, Bank B fails calibration at stage 0:
Initial failing DQ group 0
Initial failing stage: Read Calibration - VFIFO
all 8 DQS pins are detected (good news)
Seems to me to be hardware since the same core works on Bank A. Any thoughts on where to focus my debug effort? The calibration phase is run by a captive Nios CPU in the uniphy ddr3 core, and as a result is indecipherable. I have no idea how to find out what is going wrong with signaltap..