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On a custom Stratix IV board, I have two independent DDR3 banks, A and B.
Bank A works fine, Bank B fails calibration at stage 0:- Initial failing DQ group 0
- Initial failing stage: Read Calibration - VFIFO
- all 8 DQS pins are detected (good news)
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How wide is your interface? x64?
Is it the top edge controller that fails?
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