Using Stratix 10 Native PHY IP, I am interfacing to custom PCIe Logic and custom PCS to transmit PCIe like traffic using transceiver lanes. Here, I have some concerns on Electrical IDLE.
1) As per my understanding, Electrical IDLE can be achieved if the transmitter FIFO becomes empty. Whether my understanding is correct? or any other mechanism should be followed to achieve electrical IDLE?
2) Once the transceiver is out of Electrical IDLE do I need to re-calibrate the transceivers? Also, the word align logic should be re-run to align the word boundary (currently using bit slip logic to align the data word for the first time) after exiting the Electrical IDLE state?
Hi @SengKokL_Intel ,
1) As I understand the spec, in electrical IDLE state, the common mode voltage shall be maintained in the serial lines. So, with respect to S-10 transceiver, in what way I can maintain common mode voltage in the transceiver serial line, but no toggling.
2) "the transceiver does not require to perform re-calibration but the word alignment has to re-run. " Now I understand and agree with this statement.