I am using Stratix 10 SoC dev kit and testing the transceiver with FMC loopback card.
I tested with the Board test System and all are looking fine with BER = 0.
Even I opened the FMCA project available in the Dev kit example design and checked with transceiver toolkit for BER and it is showing Zero with some of the channels (GXT) running @ 25Gbps and GX channels running @ 17Gbps.
After that I created a simple project with Native PHY, ATX PLL and reset controller for one channel of Bank 1D (TX channel 0 and RX channel 0) . I am using the 644.53125MHz clock @ 1D bank reference clock pin from FMC loopback card. With this project Transceiver toolkit is locking and BER = 0. In the same project (PCS-PMA width is 64 bit with enhanced PCS or PCS direct) , I send 64-bit Incremental pattern and I expect the same to be looped back as I have inserted the FMC loopback card. But, I see only few incremental data I am able to see in RX parallel data bus. All other status looks fine. rx/tx_cal_busy = 0, rxlockedtodata = 1, tx_ready=1, rx_ready=1. rxlockedtoref is toggling randomly.
Even I checked with seriallpbken =1, with this none of the data in rx parallel data bus are matching with that of tx parallel data.
Can anybody suggest what settings migh be wrong in the PHY config.?
Attached the related .ip files for the review.
I checked the design achieve, I could not find any connection issues. But do let me test in hardware. Will update you in a day or two.
Hi @NathanR_Intel ,
Thank you for the update.
We came to know that Enhanced PCS and PCS direct doesn't support word aligner by default. With this info. I changed the Native PHY config to Enhanced PCS and enabled RX bitslip feature and port.
Now, I am sending known pattern first and checking the reciever whether it is able to lock for the first time. My observation is it is not locking without bit slip. I am pulsating the bitslip port until rx aligns for the known pattern. Once bitslip is done, then I start transmitting the incremental data.
Also, one more change I have done in native phy is change the "RX adaptation mode" to adaptive from Manual.
With this, I am able to receive the data continuously @20.625Gbps without missing any data.
Please let me know if you have any suggestion on meeting the timing. It will help us with our final implementation using startix10 FPGA.