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How to set Number of Pages and Size if Address page in PCIe (Qsys)

Altera_Forum
Honored Contributor II
981 Views

Hi Everyone, 

 

I have had a lot of problems with PICe in Qsys and I suppose the problem is the configuration of Size of Address Page and Number of Pages. Please if someone could help me... 

 

According with some posts and the PCIe CORE manual, I have did some configurations on my system, but I don't know if I understood how to set this parameters. I will try explain my system and the configurations that I did, and if someone could check what I did I will really appreciate. 

 

4 BARS configured - BAR1_0 => 64 bits 

- BAR2 => 32 bits 

- BAR3 => 32 bits 

 

So I set 4 pages, because I have 4 BARS, is it right? 

 

I mapped the addresses of the slaves using the following number of bits (BAR0_1 => 11 bits, BAR2 => 12 bits, BAR3 => 11 bits). So looking the PCIe IP MANUAL, I realized that I could use the the Size of Address Page as 18bits (256kBytes), because: 

 

Slave Base Address => 12bits. 

High => 2 bits (4 Address Page) 

Low => 18 bits (Size Address Page) 

 

In order to have 32 Avalon Address bits. I did this configurations and my system is now working. Is this correct? I'm thinking the right way? 

 

Thanks for helping 

 

Filipe
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1 Reply
Altera_Forum
Honored Contributor II
116 Views

Eh? Are you confusing the configuration of the hardware that generates PCIe cycles with the BARs? 

The size of BAR is automatically set so that it is large enough to allow another PCIe master to access any of the connected Avalon slaves. 

The PCIe slave logic looks at the high address bits in a received PCIe transfer to determine which BAR it is for, then uses the low bits as an offset within the selected Avalon slave. If the BAR references multiple Avalon slaves then high Avalon address bits will be generated if they are not needed to select between the Avalon slaves.
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