How to set the LVDS SERDES intel FPGA IP for receiving mini-LVDS signal

[BXia]

Hi,

I'm using the LVDS SERDES intel FPGA IP to receive Mini-LVDS signal, I need to receive 2 data by a clock, however, the minimum SERDES factor is 3, so how to set the IP, or anything else I need to set?

Is there a Mini-LVDS example for reference?

Thanks in advance.

[YuanLi_S_Intel]

Hi, it would be better if you could choose mini-LVDS IO standard in FPGA to interface with mini-LVDS input.

[YuanLi_S_Intel]

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