FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6359 Discussions

How to simulate DDR2 using ModelSim-Altera

Altera_Forum
Honored Contributor II
‎08-17-2009 05:28 AM
890 Views

Can anyone please help me to solve this problem? 

 

I have compiled all the files successfully in modelsim. While simulating DDR2, the signals mem_dq and few other signals are undefined.  

 

Kindly explain the steps to simulate DDR2 IPcore 

 

Please help me...... 

 

Thanks & Regards 

VV
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎09-30-2009 05:12 AM
199 Views

If you are using the megafunction to generate DDR2 controller,  

then modelsim testbench and memory model should have generated. 

 

That make life a lot easier.
0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.