How to test user logic

[Altera_Forum]

Hi,everyone, 

I wrote a user logic to make Nios II read data from a fifo.The ports defination as follow: clk, resetn, //interface to Avalon chip_select, address, write_n, write_data, read_n, read_data, //interface to fifo fifo_indata, rdclk, //fifo read clock rdreq //fifo read requst signal   I also wrote the head file of register for Nios to read or write the registers.   How can I test my own module?Are there some steps I can follow? And how can I make sure how many cycles the Avalon needs to read from the registers?    Help me ,please. Thanks.

[Altera_Forum]

You will need to create a test bench (Ideally in Verilog) to stimulate your design. 

 http://www.asic-world.com/verilog/art_testbench_writing2.html#writing_a_testbench  Has some good pointers as to how to write a testbench.  My advice would be start simple but design for flexibility.