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SPI Core Question

Altera_Forum
Honored Contributor II
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Hi, 

I've already gotten my own SPI code working for this project, but I have been asked to find out more about Altera's SPI Core, namely the one described in www.altera.com/literature/hb/nios2/n2cpu_nii51011.pdf (http://www.alteraforum.com/forum/www.altera.com/literature/hb/nios2/n2cpu_nii51011.pdf

 

I don't see this in the list of available Megafunctions in Quartus 7.2. We are not using NIOS. Can we still use this core? 

 

 

Thanks very much for any help. 

-JC
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Altera_Forum
Honored Contributor II
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Yes but you might have to do a little extra work. The SPI core is an SOPC builder component. You can create an instance of SOPC builder without using the NIOS processor. So there are a couple of ways you could do this: 

 

1 - Generate an instance of SOPC builder that includes the SPI core. You'll then have to create a module that exports the avalon bus so that you can connect to it outside of SOPC builder. So you then create an instance of this SOPC system and connect your control signals to the exported avalon bus. 

 

2 -Use SOPC builder as described above to generate the code. However, go ahead and drop in a NIOS processor and connect it to the SPI core. rather than exporting the avalon bus Once you generate the SOPC system, you'll end up with all of the generated verilog files for your SOPC system. One of those files will be your SPI instance. Simply use this file to create an instance of your SPI core rather than creating an instance of the entire SOPC system. In this case you're just using SOPC builder as a code generator. 

 

Either way, you will have to implement an Avalon master to be able to control the core. 

 

If it were me and I'd already written my own core, I would continue to use that. 

 

Jake
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Altera_Forum
Honored Contributor II
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Thank you for the reply, it was very helpful. 

 

-JC
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