My custom master component is connected to DDR slave in Platform designer(Qsys). I want to write data on to ddr from the custom master component, for this I should write the Verilog code to access the DDR right? Custom component having Avalon MM interface. Please give me suggestions on this. I have written a piece of code . Please check and let me know if it needs any correction.
For Avalon-mm master spec, you can refer to this user guide https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf, Figure 7 to understand read and write transfer timing. In your case, response signal is an option and not required.
Figure 7 to understand read and write transfer timing. In your case, response signal is an option and not required.
Yes, this will help me.
Thanks for the suggestion.