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URN
Novice
774 Views

How to write/read to external DDR from custom Qsys component (custom IP).

I could write some data on to external DDR from HPS Linux C . I want my custom component to read that data from DDR , perform some operation and put the result back to DDR at different memory location. Here, DDR should be dual port right? One slave port connected to HPS master axi bus and another slave port to custom component master? Here custom component should have Avalon mm interface?? Appreciate your help..

 

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9 Replies
KennyT_Intel
Moderator
220 Views

Hi,

 

You cannot do that, HPS to DDR only have one dedicated path. You have to control your memory location in the HPS C code itself.

 

 

Thanks

URN
Novice
220 Views

Hi, then how do I access the data in DDR from my custom component? I want to read the data on the DDR from custom component. I am newbie in Platform Designer usage. Please guide me .. Thank you
URN
Novice
220 Views

Hi, here I am talking about the DDR connected to FPGA part of Arria 10 SOC FPGA. How can I write and read FPGA DDR. Later I want to access this DDR content from custom component. Give me suggestions on this. Please check the image attached.

 

Many Thanks

URN
Novice
220 Views

Hi, then how do I access the data in DDR from my custom component? I want to read the data on the DDR from custom component. I am newbie in Platform Designer usage. Please guide me .. Thank you
sstrell
Honored Contributor II
220 Views

A single slave can be accessed by multiple masters. You don't need dual slave ports, but your custom component does need a master interface (Avalon or AXI). Simply click the appropriate dots in the System Contents tab of Platform Designer, or right-click the slave interface of the DDR, go to the Connections submenu, and make the connections there. Check out this online training:

 

https://www.intel.com/content/www/us/en/programmable/support/training/course/oqsysfinish.html

 

#iwork4intel

 

SVN
Beginner
220 Views

hi, Thanks for the response,

A single slave can be accessed by multiple masters. You don't need dual slave ports, but your custom component does need a master interface (Avalon or AXI). You are right. I will check out the online training. Hope to find the solution soon...

 

Many Many Thanks

 

 

 

 

URN
Novice
220 Views

hi,

My custom master component is connected to DDR slave in Platform designer(Qsys). I want to write data on to ddr from the custom master component, for this I should write the Verilog code to access the DDR right? Custom component having Avalon MM interface. Please give me suggestions on this.

 

thank you

KennyT_Intel
Moderator
220 Views

HPS to DDR will have dedicated path for the interconnect in Qsys. You can try to use the custom component to access by sharing the master with the HPS. However, it might hit the fitter error since HPS to DDR have dedicated path. What I would suggest is use your C code in HPS to control the address writing for the DDR.
URN
Novice
220 Views

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