I could write some data on to external DDR from HPS Linux C . I want my custom component to read that data from DDR , perform some operation and put the result back to DDR at different memory location. Here, DDR should be dual port right? One slave port connected to HPS master axi bus and another slave port to custom component master? Here custom component should have Avalon mm interface?? Appreciate your help..
Hi, here I am talking about the DDR connected to FPGA part of Arria 10 SOC FPGA. How can I write and read FPGA DDR. Later I want to access this DDR content from custom component. Give me suggestions on this. Please check the image attached.
A single slave can be accessed by multiple masters. You don't need dual slave ports, but your custom component does need a master interface (Avalon or AXI). Simply click the appropriate dots in the System Contents tab of Platform Designer, or right-click the slave interface of the DDR, go to the Connections submenu, and make the connections there. Check out this online training:
hi, Thanks for the response,
A single slave can be accessed by multiple masters. You don't need dual slave ports, but your custom component does need a master interface (Avalon or AXI). You are right. I will check out the online training. Hope to find the solution soon...
Many Many Thanks
My custom master component is connected to DDR slave in Platform designer(Qsys). I want to write data on to ddr from the custom master component, for this I should write the Verilog code to access the DDR right? Custom component having Avalon MM interface. Please give me suggestions on this.