FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5982 Discussions

I can't run synthesis with the encrypt_1735 output in Quartus

RSpaa
Beginner
577 Views

Hello,

I'm using the encrypt_1735 utility and it encrypts from what I see. However, when I try to run synthesis in Quartus, red X's appear over the steps, but no pop up appears. Am I doing something wrong running the encrypt utility or is there a separate step in order to run the encrypted sources in Quartus? Thanks!

0 Kudos
1 Reply
RichardTanSY_Intel
168 Views

I think I got it. You could cross check with my steps. In this case, I am using a simple design called counter.v

  1. Encrypt the design with IEEE 1735. Command line used:  encrypt_1735 --quartus --language=verilog counter.v
  2. File counter.vp will be generated in the file folder.
  3. Open a new project, add counter.vp in the project. Set it as top-level entity.
  4. Right click on the counter.vp. Select Properties. Ensure the Type: Verilog HDL File.
  5. Run Analysis & Synthesis.

 

Hope it helps.

Reply