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I can't run synthesis with the encrypt_1735 output in Quartus



I'm using the encrypt_1735 utility and it encrypts from what I see. However, when I try to run synthesis in Quartus, red X's appear over the steps, but no pop up appears. Am I doing something wrong running the encrypt utility or is there a separate step in order to run the encrypted sources in Quartus? Thanks!

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I think I got it. You could cross check with my steps. In this case, I am using a simple design called counter.v

  1. Encrypt the design with IEEE 1735. Command line used:  encrypt_1735 --quartus --language=verilog counter.v
  2. File counter.vp will be generated in the file folder.
  3. Open a new project, add counter.vp in the project. Set it as top-level entity.
  4. Right click on the counter.vp. Select Properties. Ensure the Type: Verilog HDL File.
  5. Run Analysis & Synthesis.


Hope it helps.