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Avinash_S_Intel
Employee
403 Views

Stratix 10 GX: "Non Power of Two" Interconnect Fabric

Hi,

 

In my design, there is a need to access DDR4 EMIF by multiple Avalon Master Interfaces. Also, the design uses its own ECC logic, hence, i have disabled the EMIF ECC logic.

 

EMIF's Avalon Slave interface provides a data bus of 576 bits wide (ratio 1:4 and DDR4 DQ being 72 bits).

 

I have used Avalon MM Pipeline Bridges (data width 576 bits) to connect to EMIF Avalon Slave. When i connect one bridge to EMIF's Avalon Slave i see no issue.

 

When i try to add another bridge, i get an error saying the data widths have to be power of 2.

 

Is there a way to make the Interconnect Fabric work with "non-power of two" widths?

 

Regards,

Avinash

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2 Replies
NurAida_A_Intel
Employee
47 Views

Dear Avinash,

 

Before I explain further on the issue, there are few aspects which impact your architecture/design :

 

1.     Avalon Interface spec - says non power of 2 data widths are not supported, and this to address typical bus interface scaling. For more details you can refer to this Avalon Interface spec:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf

 

2.     Platform Designer Interconnect - Support only Avalon interfaces with power of 2 data bus width for multiple buses interconnect. This allow design flexible burst adaptations scaling with data width - e..g 1:2,1:4,1:8, 1:16 etc. There is an exception - non power of 2 bus interconnect is supported in 1:1 connection.  

 

3.     Platform Designer documentation - section 1.6.1.1. Support for Avalon-MM Non-Power of Two Data Widths explain this: 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-platform-designer...

 

The reason of the error is because you are using 72bits interface. If you convert all 72bits to local interface (quarter rate) data width it is 72X8 = 576 which is not power of 2. Thus, for 72bits interface, usually the extra 8 bits is user for error detection and we only use 64 bits for data. To execute this approach, you have to tick “enable error detection and correction logic with ECC” in your S10 EMIF GUI. After this tick, it will convert the amm data width from 576 to 512 which is power of 2 and this remove the error as above. So, either make the interface 64 bits wide or keep it as 72 bits wide and enable ECC to get rid of this issue.

 

To keep things simple for now and avoid the complexity of ECC, I'd recommend that you change the memory interface bus width to 64 bits and then the Avalon busses will be a power of 2 width and connect up without problems in QSYS.

 

Hope this make sense to you.

 

Thanks.

 

Regards,

NAli1

Avinash_S_Intel
Employee
47 Views

Hi NAli1,

 

Thanks a lot for your response and i agree to your comments on my issue.

 

2.     Platform Designer Interconnect - Support only Avalon interfaces with power of 2 data bus width for multiple buses interconnect. This allow design flexible burst adaptations scaling with data width - e..g 1:2,1:4,1:8, 1:16 etc. There is an exception - non power of 2 bus interconnect is supported in 1:1 connection. 

 

Now, i am trying to use one Avalon MM Pipeline Bridge and connect to EMIF. I have kept the Avlon MM Data width 576. This will be the exception which you have mentioned - 1:1 connection.

  1. I see HDL generation in this case goes through without issue.
  2. Testbench generation with BFMs errors out as the Avalon MM BFM again does not support non power of two width

 

Is there a way to work around this limitation of the BFM?

 

Since i do not have a way of providing access to multiple Avalon MM interfaces (non power of two) to DDR4 via EMIF, i intend to implement a Avalon MM Multiplexer in front of the Avalon MM Pipeline Bridge to provide access to two MM interface access to DDR4 via the EMIF. I plan to use Avalon interface's "waitrequest" signal to hold one of the interfaces while the other is accessing the EMIF.

Any suggestions on the implementation of this MUX is most welcome.

 

Below is a picture of the implementation i plan to execute.

 

Regards,

Avinash (Intel Employee)

 

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