IP_XACT_REGISTER_MAP for PCIE And DDR controller

[10]

Hi ,

   Need to create IP_XACT_REGISTER_MAP for PCIE and DDR controller.

can anyone tell me the procedure?

i need ipxact_register_map for below format 

Thanks in advance

indirapriya

[SengKok_L_Intel]

Hi Indirapriya,

In order to better assist you, would you please do let us know what FPGA device and Quartus version that you are using?

Regards -SK

[10]

Hi,

   Stratix 10DX Device

   part no : 1SD280PT2F55E1VG

Quartus version: 20.2

can you please any one tell me the procedure or scripting also?

Thanks in Advance

Indirapriya

[SengKok_L_Intel]

Hi,

I can't find any IP-XACT detail from the PCIe IP documentations.

From the link below, it states that the IP-XACT is NOT supported.

https://www.intel.com/content/www/us/en/programmable/products/intellectual-property/ip/interface-protocols/m-pci-express-protocol.html

Regards -SK

[10]

Hi Sengkok,

   thanks for your fast reply.

What about IP_XACT_REGISTER_MAP for DDR controller?

I was created example design of PCIe_Multi channel DMA Express and DDR controller. In that pcie_ed.ipxact and ed_sim_emif.ipxact file was generated.

here it was not mentioning the Registers of PCIe Multi channel DMA and  DDR controllers. It shows only bus interface and port map of that

if possible please arrange webx meeting and this is my highest priority 

<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Altera Corporation</ipxact:vendor>
<ipxact:library>pcie_ed</ipxact:library>
<ipxact:name>pcie_ed</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
<ipxact:name>refclk</ipxact:name>
<ipxact:busType vendor="altera" library="altera" name="clock" version="20.2"/>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="20.2"/>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>clk</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>refclk_clk</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:slave/>
<ipxact:parameters>
<ipxact:parameter parameterId="clockRate" type="longint">
<ipxact:name>clockRate</ipxact:name>
<ipxact:displayName>Clock rate</ipxact:displayName>
<ipxact:value>100000000</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="externallyDriven" type="bit">
<ipxact:name>externallyDriven</ipxact:name>
<ipxact:displayName>Externally driven</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="ptfSchematicName" type="string">
<ipxact:name>ptfSchematicName</ipxact:name>
<ipxact:displayName>PTF schematic name</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:busInterface>
<ipxact:busInterface>
<ipxact:name>pcie_rstn</ipxact:name>

Thanks in Advance

Indirapriya

[SengKok_L_Intel]

I don't see the DDR controller support the IP XACT either. I will double-check with the DDR specialty and get back to you by early next week.

[BoonT_Intel]

I believe the IP-XACT is used internally for file generation purposes and it does not support to use externally.

[SengKok_L_Intel · Accepted solution]

Thanks, Boon. Yes, DDR and PCI-E IP do not really support the IP_XACT at this moment.

[SengKok_L_Intel]

If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 

[10]

Hi

I need support regarding IP_EXACT reg_map and can you please arrange webx meeting.

Thanks

Indirapriya