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SLabe
Partner
1,562 Views

PCIe Example Design Simulation Failing

Unsing Quartus 18.1 Pro. Generated Gen2x1 or Gen3x4. When compiling in modelsim, I get the following:

# Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018

# Start time: 11:31:38 on Nov 06,2018

# vlog -reportprogress 300 -sv ../../../ip/pcie_example_design_tb/pcie_example_design_inst_board_pins_bfm_ip/altera_conduit_bfm_181/sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq.sv -L altera_common_sv_packages -work altera_conduit_bfm_181 

# ** Error: (vlog-7) Failed to open design unit file "../../../ip/pcie_example_design_tb/pcie_example_design_inst_board_pins_bfm_ip/altera_conduit_bfm_181/sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq.sv" in read mode.

# No such file or directory. (errno = ENOENT)

# End time: 11:31:38 on Nov 06,2018, Elapsed time: 0:00:00

# Errors: 1, Warnings: 0

 

When checking the path, the file does not exist. Thank you.

0 Kudos
6 Replies
AnandRaj_S_Intel
Employee
77 Views

Hi,

 

We acknowledge the issue and will gt back on this,

Also checked with Modelsim 10.6C which gives same error.

 

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

SLabe
Partner
77 Views

Based on my investigation, it's probably not due to Modelsim version... It looks more like a qsys generation problem. On that, note that I've tried 17.1 Pro as well with the same outcome. When examining the example design log I do see:

Info: pcie_example_design_inst_board_pins_bfm_ip: "Generating: pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq"

 

But the file is nowhere to be found... I've tried running as admin to rule out the permissions, I looked into the temp folder it appears to use but it looks like its hidden in a _db file.

 

Thanks your help,

JosephC_Intel
Moderator
77 Views

Hi Slabe,

 

We've reported this issue into our bug data entry. Currently under assigning stage. If there is further details obtained, I'll keep you posted.

 

Thanks,

Joseph

Intel Customer Support

610012

 

AndyN
New Contributor I
77 Views

By any chance, are you running on Windows? I had the same (or similar) problem a while ago and it came down to the path length ending up being stupidly long...

SLabe
Partner
77 Views

Hi Andy, yes Windows. I was actually careful of that and generated the example design at the C:/ level.

 

Also, there is a pkg file generated at the same depth... so should not be an issue. An Intel FAE colleague also reported that he had observed the same issue...

 

Thanks,

41 Views

Hi, SLabe,I got the same simulatioan error and indeed could not generate the simulation file named "pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq.sv" . OS of my computer is Win10 , version of  Quartus Prime Pro Eniton is 18.1 and simulation tool is  Questa Sim-64 10.6c. I got error messages as follows, do you know how to fix it now? Thank you very much.

# vlog -reportprogress 300 -sv ../../../ip/pcie_example_design_tb/pcie_example_design_inst_board_pins_bfm_ip/altera_conduit_bfm_181/sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq.sv -L altera_common_sv_packages -work altera_conduit_bfm_181
# ** Error: (vlog-7) Failed to open design unit file "../../../ip/pcie_example_design_tb/pcie_example_design_inst_board_pins_bfm_ip/altera_conduit_bfm_181/sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq.sv" in read mode.