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IP compiler for PCIE has changed in v13.1 and it broke my design. How to fix it?

Altera_Forum
Honored Contributor I
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Hello, 

 

I was recently upgrading a QSYS subsystem from version 11.1sp2 to 13.1. The design uses IP compiler for PCI express. When I regenerated the system, my top level design complained about two ports missing. When I went back to the subsystem, I noticed that Altera split one conduit 'pipe_ext' into 'pipe_ext' and 'powerdown'. (See fig pcie_compiler_11.1 and pcie_compiler_13.1). The figure pcie_compiler_13.1_hierarchy shows the list of signals within the conduit. 

 

Is there a way to create a new component which combines these two conduits and generates one output conduit? I want to avoid changing the instantiationat top level module. 

I tried doing it using the GUI, using an HDL file to generate signals, as well as manually adding the signals. I have attached the HDL file. 

 

I get the following errors: 

Error: System.pcie_combine_coe_0.powerdown/PCIE_COMPILER.powerdown: PCIE_COMPILER.powerdown has a pll_powerdown signal, but pcie_combine_coe_0.powerdown does not. Error: System.pcie_combine_coe_0.powerdown/PCIE_COMPILER.powerdown: PCIE_COMPILER.powerdown has a gxb_powerdown signal, but pcie_combine_coe_0.powerdown does not. Error: System.pcie_combine_coe_0.powerdown/PCIE_COMPILER.powerdown: pcie_combine_coe_0.powerdown has a export signal, but PCIE_COMPILER.powerdown does not. Error: System.pcie_combine_coe_0.powerdown/PCIE_COMPILER.powerdown: pcie_combine_coe_0.powerdown has a export signal, but PCIE_COMPILER.powerdown does not.  

A snapshot of the errors is in component_error.PNG 

 

Note: I used the same signal names as the ones in the original PCIE_COMPILER conduits. It still complains about them. I get similar errors when I connect 'pipe_ext' from PCIE_COMPILER to 'pipe_ext' of pcie_combine_coe_0. 

 

Any help would be appreciated.
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