IP core optimization

[Altera_Forum]

Hi everyone, 

 How can I optimize any IP core for Altera FPGA technology? What kind of care needs to be taken when optimizing for particular FPGA technology or ASIC?

[Altera_Forum]

Anyone who knows it, please help me. I would like Altera Gurus to help me out with this problem.

[Altera_Forum]

I've difficulties to hear a specific question.

[Altera_Forum]

Alright! Lets make it general, what should be an approach to optimize cores? i.e. does it make difference in optimization if I take off the shelf memory core or altera's megacore like altsyncram?

[Altera_Forum]

Sorry, Ketan, but it's still not clear what you want to do. Optimizing something for FPGA implementation could mean to describe the logic in a way that the synthesis tools is able to implement it according to your needs that you still haven't said. Do you want highest speed? Then try to pipeline the logic so that only one LUT is needed between two registers stages. Or do you want smallest area? Or lowest power? You question is not specific enough by now.

[Altera_Forum]

Altsyncram is a good example for the fact, that IP has to consider particular hardware properties. Internal RAM blocks are showing some implementation differences between FPGA families (e.g. which RAM ports are registered). Furthermore, not all internal RAM features are accessible from HDL (e.g. dual port with port width translation), an IP has to use Altera specific libraries to utilize it. If the IP is also intended for use with other vendor's FPGA, more differences come into play. 

 This is all about basic porting, optimizing probably means more.

[Altera_Forum]

Thanks Harald! I am re-designing a existing fast Ethernet MAC IP (with limited feature to incorporate into an embedded system) which needs to be fit in to Altera's small FPGA which should be optimized in both speed and area. I would like to reduce its size to round about less than 1000 LEs and 4-6 Kb internal memory usage. 

Thanks Frank! Can you please tell me which parameters need to be taken care of when optimizing IP cores for a specific vendor FPGA, for a time being lets take only Altera's FPGAs.

[Altera_Forum]

--- Quote Start ---  I am re-designing a existing fast Ethernet MAC IP... which needs to be fit in to Altera's small FPGA which should be optimized in both speed and area. I would like to reduce its size to round about less than 1000 LEs and 4-6 Kb internal memory usage.  --- Quote End ---     In the Quartus handbook, see Volume 2, Section III, "Area, Timing and Power Optimization".  Within Quartus, run "Resource Optimization Advisor" and "Timing Optimization Advisor" at "Tools --> Advisors".  Note that some optimizations that help area hurt speed and vice versa.

[Altera_Forum]

Hi I wrote http://nibz.googlecode.com using Quartus II, in the current incarnation nibz12.vhd the "ALTERA" generic is not used anywhere. The LUT usage is mainly controlled by the VHDL sythesizer setting of area, balanced or speed. The area option even provides more speed sometimes, but enable register retiming etc to get the exta nano second. Avoid long chains of carry propergation. Nibz although a 34 state state machi9ne, renders as a 5 state state machine in one hot technology. Why, I don't know. 

 So 4-LUT or arithmetic and/xor double 3-LUT (I think) *2 in each logic element with one general register/latch.   Memory: use registered read for generality.   cheers jacko

[Altera_Forum]

Thanks Brad! I will look into the Handbook, but I wanted to know if there is any thumb rule!

[Altera_Forum]

--- Quote Start ---  ... I wanted to know if there is any thumb rule!  --- Quote End ---    The optimization advisors in Quartus that I mentioned cover most of the things that I usually try first like optimization technique in Analysis & Synthesis and physical synthesis for performance in the Fitter. The advisors also suggest things that I rarely bother with such as optimizing state machine encodings (probably not worth the trouble unless you have a huge state machine or your worst timing violations are in a state machine) and LogicLock (helps speed in only a few designs, and can make things worse if done wrong). Start with the advisor recommendations that are the easiest to try. Many are simple setting changes that can be done right in the advisor window.

[Altera_Forum]

Thanks once again Brad! But I was really looking for something which can be done in HDL when designing any core. I guess it is huge area of concern which requires time and patience.