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DDR HP controller read data valid signal is not aligned with read data

Altera_Forum
Honored Contributor II
‎07-30-2008 02:00 AM
1,186 Views

i use DDR hp controller to interface a micron ddr chip mt46v32m16, two chips to form 32bit width. 

but when i send out read request and wait the read data and read data valid sinal, they come back , but not aligned, 

local_rdata_valid is 11 clocks later tham local_rdata, 

how can that happen? anybody knew this issue?/
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Altera_Forum
Honored Contributor II
‎08-19-2008 09:34 AM
466 Views

I encountered the same question as you. Hope someone can solve it !

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Altera_Forum
Honored Contributor II
‎08-23-2008 03:34 AM
466 Views

hi, there, 

i have solved my problem, it just need a longer time reset, for example 200ms, on my board, i think this is caused by my Vref dc-dc chip don't output right when i download my new sof file for a while. 

hope useful for u!
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