DDR HP controller read data valid signal is not aligned with read data

[Altera_Forum]

i use DDR hp controller to interface a micron ddr chip mt46v32m16, two chips to form 32bit width. 

but when i send out read request and wait the read data and read data valid sinal, they come back , but not aligned, local_rdata_valid is 11 clocks later tham local_rdata, how can that happen? anybody knew this issue?/

[Altera_Forum]

I encountered the same question as you. Hope someone can solve it !

[Altera_Forum]

hi, there, 

i have solved my problem, it just need a longer time reset, for example 200ms, on my board, i think this is caused by my Vref dc-dc chip don't output right when i download my new sof file for a while. hope useful for u!