tDSS violation in DDR2 HP controller function simulation

[Altera_Forum]

Hi everyone: 

 I have an Arria GX Dev board. The DDR2 module on it is MICRON 32-MByte x 16 DDR2 SDRAM operating at 233MHz.But I can't access DDR2 SDRAM with DDR2 High-Performance controller 7.2 correctly.    I have download the verilog model of the 512M DDR2 sdram from micron.I created a test project followed the ddr2 hp controller user guide.   When I run function simulation of example design with the micron model,the testbench always report that there are some tDSS violations when write continued data to DDR2 sdram. The write data can't be captured correctly with DQS.   I have checked the DDR2 sdram parameters for ddr2 hp controller. How can I sovle my problem?   Thanks!

[Altera_Forum]

Did you properly configure the Micron DDR2 simulation model? The model is used for every speed grade part so you have to configure the settings file to match your DDR2 controller. 

 Jake