Implementaion of Megacore generated DDR2 SDRAM controller

[Altera_Forum]

Hi There 

 I have a StratixII GX board and I need to prove our DDR2 core on this board. Is it possible to port our core to altmemphy and try implementation and generating bit file to prove on board. As per altmemphy document, the calibration logic is encrypted. With this encrypted module, can we generate bit file.   Or I would request you to tell me that how best I can use Altmemphy to prove our core on the StratixII GX board  Thanks

[Altera_Forum]

DDR and DDR2 SDRAM Controller's cotrol logic is encrypted. I believe I can replace it with our core and try out. But the problem here is local_rdata_valid signal is coming out of control logic. Since the datapath does the read operation, hence datapath should give the associated rdata_valid signal with the control_rdata.  

  Please reply if anybody there has got some idea

[Altera_Forum]

The controller is the one who issued the read and is responsible for knowing when the read data from the data path is valid. 

 Jake

[Altera_Forum]

Would comment on your reply after I get the reply for my first post"As per altmemphy document, the calibration logic is encrypted. With this encrypted module, can we generate bit file. "