I am implementing a PCIe root port on a Stratix 10 MX FPGA development kit using ST-Avalon IP and I face several Issues doing that.
Do you have an example design for the root-port?
I already found for PCIe end-point in the board documentation but nothing about the root port.
Thank you very much for your help
This is to let you know that I don't aware there is a demo/full design of PCIe Root Port on S10 MX FPGA dev Kit. For high-level interface design, you can generate it from the IP GUI (configure in the Example design tap, and then click generate example design).