FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5878 Discussions

Implementation of a PCIe root port on stratix 10 MX devkit.

AKhel1
Beginner
142 Views

Hello,

 

I am implementing a PCIe root port on a Stratix 10 MX FPGA development kit using ST-Avalon IP and I face several Issues doing that.

Do you have an example design for the root-port?

I already found for PCIe end-point in the board documentation but nothing about the root port.

 

Thank you very much for your help

Best regards

Amine

0 Kudos
1 Reply
SengKok_L_Intel
Moderator
94 Views

Hi,

 

This is to let you know that I don't aware there is a demo/full design of PCIe Root Port on S10 MX FPGA dev Kit. For high-level interface design, you can generate it from the IP GUI (configure in the Example design tap, and then click generate example design).

 

Regards -SK

Reply