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Beginner
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FFT IP core sink_ready never gets asserted

I'm attempting to simulate the FFT IIP core, using buffered burst mode. However, sink_ready never gets assertedmylogic.PNG

I would expect sink_ready to go high, as soon as reset is de-asserted (set to 1), as per the datasheet

dslogic.PNG

 

Perhaps I am not simulating the fft ip correctly? After running RTL Simulation and Modelsim is loaded, I close the simulation Modelsim initially loads (I don't understand what to do with the initial simulation as it has no stimulus?). I then load my own testbench which is included in the project.

 

I've attached an archive of my project.

 

Thanks for reading

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Hi,

 

As I understand it, you observe some issue when trying to perform simulation with FFT IP. I have tried to look into your attached QAR but not sure the step to run the simulation to reproduce your observation. Would you mind to share with me your simulation ZIP folder as well as detailed steps to perform simulation and replicate your observation in Modelsim?

 

Thank you very much.

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Beginner
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Thanks for your response. I've decided to just simulate using signal tap instead as I've been having too many problems with altera-modelsim

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Hi,

 

Thanks for your update. Sorry for the inconvenience.

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