FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5746 Discussions

FFT IP core sink_ready never gets asserted

Rtemple
Beginner
173 Views

I'm attempting to simulate the FFT IIP core, using buffered burst mode. However, sink_ready never gets assertedmylogic.PNG

I would expect sink_ready to go high, as soon as reset is de-asserted (set to 1), as per the datasheet

dslogic.PNG

 

Perhaps I am not simulating the fft ip correctly? After running RTL Simulation and Modelsim is loaded, I close the simulation Modelsim initially loads (I don't understand what to do with the initial simulation as it has no stimulus?). I then load my own testbench which is included in the project.

 

I've attached an archive of my project.

 

Thanks for reading

0 Kudos
3 Replies
CheePin_C_Intel
Employee
106 Views

Hi,

 

As I understand it, you observe some issue when trying to perform simulation with FFT IP. I have tried to look into your attached QAR but not sure the step to run the simulation to reproduce your observation. Would you mind to share with me your simulation ZIP folder as well as detailed steps to perform simulation and replicate your observation in Modelsim?

 

Thank you very much.

Rtemple
Beginner
106 Views

Thanks for your response. I've decided to just simulate using signal tap instead as I've been having too many problems with altera-modelsim

CheePin_C_Intel
Employee
106 Views

Hi,

 

Thanks for your update. Sorry for the inconvenience.

Reply