Hello, I'm trying to instantiate a component of the SDI II Intel FPGA IP as a receiver, but whenever I attempt to compile the design I get the following errors:
Error (11661): Design uses HSSI PLLs that are not supported in the selected device.
Error (11666): Device "5CSEBA6U23I7" does not support "Channel PLL".
I'm using the DE10 Nano development board and Quartus Prime Lite 19.1. It says in the datasheet for the 5CSEBA6 that it supports 3G-SDI, and the IP user guide would appear to confirm this, so I'm confused why the design won't compile. I've tried multiple settings for the transceiver reference clock frequency, but I always get the same error.
Could I please get an explanation of where I'm going wrong?
As I understand it, you encounter some compilation error related to no HSSI PLL supported in the your selected device. For your information, the HSSI PLL is only available in CV GX devices. The device 5CSEBA6U23I7 that you are selecting is not a GX device. This is why during compilation, you will see the error.
Mind share with me further on the specific datasheet which mention about this device supporting HSSI PLL?
Please let me know if there is any concern. Thank you.