Hej everyone,
I have to import the OpenRISC IP into SOPC Builder.
Since it's a Wishbone master, I've designed a wrapped version in order to use it in an Avalon MM system.
Now I'm writing a TCL script that allows to customize and import the processor into SOPC-B.
I would like to know if SOPC-B requires particular information about the processor and if there are any constraints relating the customization of the processor in a SOPC-B environment. In fact it is possible to deeply modify the internal structure of the IP just activating or commenting a long list of macros. For instance it is possible:
- to have or not the instruction and/or data caches and eventually to modify their size
- to enable/disable the PIC and change the number of interrupt inputs
- to change the clock mode
- to enable/disable some extra "opcode"
- and many others
More over since the final TCL should provide a GUI with more or less the same features of the NiosII's one, I was wondering how it could be possible to let the designer chose amongst the memories already instantiated (if any) in the system to set the Reset and Exception vectors location. But which are the TCL command to get the list of the already instantiated components?
Thank you very much
