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In 100G MAC+PHY simulation tx5l_ack signal sometimes goes to zero

Altera_Forum
Honored Contributor II
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Hi, everyone! 

 

I am simulating MegaCore 100-Gbps Ethernet MAC and PHY, and have noticed some strange behavior. I am using default testbench from «example_testbenches» with adapters. Signal «tx5l_ack» in «adapter_tx» is not equal 1'b1 all the time during test ( even after lanes are syncronized ), so if I am understanding right it's not possible to get full 100% line speed, because we need to wait some ticks and duplicated data.  

 

At «Stage 1» ( when no data is transmitted ) I get 2.7 % cycles where data is not acknowledged ( so I can get only 97.3 % real throughput? ). At next stages, when data is transmited this percent getting worse. I see that «tx5l_ack» got to zero, when «tx_mii_ready» go to zero, but why it is doing this? What am I doing wrong? 

 

I noticed, that top testbench file ( alt_e100_avalon_tb.sv ) is simulating with timescale 1ps, so time period of «clk_ref» in simulation is 1550000 fs, and it's 645.161290 MHz ( when it should be 644.531250 (?) ). And «pma_clk_tx» 3874000 fs => 258.131130 MHz ( should be 257.812500 (?) ), and «tx_serial» period is 97000 fs => 10309.278350 MHz ( should be 10312.5 MHz (?) ).  

 

I changed timescale in top file to 1fs, calculate more accurate period for «clk_ref» and other clocks and got this: «clk_ref» = 644.531728 MHz, «pma_clk_tx» = 257.796540 MHz, «tx_serial» = 10309.278350 MHz, so, «pma_clk_tx» changed, and «tx_serial» don't. But this didn't solve my problem with «tx5l_ack» signal. Maybe it's just simulation bug, and in hardware it will be all ok? 

 

 

I am using ModelSim SE-64 10.0c for simulation, megacore and examples was generated in Quartus 13.0.0 build 156 ( in MegaWizard ).  

Megacore for Stratix V, with MAC RX and TX, with adapters. PHY configuration: 100Gbps: 10x10. PLL type: ATX. 

 

 

Thanks in advance.
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