In PCIe DMA reference design, export TX Slave interface to allow use in rest of FPGA

Altera_Forum · ‎08-23-2017

Extremely new to QSys and couldn't find good information by searching. :confused:

How do I export the TX Slave interface (TXS) in the attached QSys system to make it available to the rest of the FPGA design? I would like both the internal sources (rd_dcm_master and wr_dcm_master) and external sources (elsewhere in the FPGA) to be able to use this interface to master PCIe transactions. i.e., I would like QSys to create an arbiter and export one of the sources.

Thanks!

Altera_Forum · ‎10-30-2017

Hi

In order to export the TX Slave you need to create a pipeline bridge and export it out.

-First you connect the TX Slave to Master pipleline bridge

-Second export the Slave pipleline bridge

Altera_Forum · ‎10-30-2017

Hi

In order to export the TX Slave you need to create a pipeline bridge and export it out.

-First you connect the TX Slave to Master pipleline bridge

-Second export the Slave pipleline bridge

Regards,

WaiMun

[‎10/‎30/‎2017 1:20 PM] Tan, Kenny Ker Wei:

(This message was posted on behalf of Intel Corporation)

Altera_Forum · ‎10-30-2017

Thank you!