DDR3 RESET implementation overview

[Altera_Forum]

Dear Gurus, 

 We are recently having invalid data when we reset our DDR3. Below there is Altera Documentation and my questions. We are using Quartus 11.1, with StratixIII-EP3SL70-F780C4   DDR3 SDRAM Controller with UniPHY Interfaces   global_reset_n reset input Asychronous global reset for PLLand all logic in PHY   soft_reset_n reset input Asychronous reset input. Resets thePHY, but not the PLL that the PHYuses.   afi_reset_n reset output(PLL master) Reset output ofthe AFI interface. This interface isasserted when the PLL loses lock orthe PHY is reset.     Questions: 1- Should we connect the power up reset input(Input of FPGA coming from PCB) to global reset_n? 2- Should we use afi_reset_n output at all? 3- Should we connect the afi_reset_n output of the FPGA to global reset_n not to soft reset_n because we want to reset the PLL it is out of lock? 4- When should we use soft_reset_n, what is the advantage of using soft_reset_n, does it allow to recalibrate DDR3? 5- Should we use calibration success or calibration fail in the reset routine?  regards Drogio

[Altera_Forum]

1- Should we connect the power up reset input(Input of FPGA coming from PC to global reset_n?Yes. 

2- Should we use afi_reset_n output at all?Yes, The afi_reset_n will asserted once the PLL locked  3- Should we connect the afi_reset_n output of the FPGA to global reset_n not to soft reset_n because we want to reset the PLL it is out of lock? No  4- When should we use soft_reset_n, what is the advantage of using soft_reset_n, does it allow to recalibrate DDR3? Yes, it will reset to memory  5- Should we use calibration success or calibration fail in the reset routine?No, those signal is to monitor the calibration status.  Regards, WaiMun   (This message was posted on behalf of Intel Corporation)

[Altera_Forum]

This is a duplicate of http://alteraforum.com/forum/showthread.php?t=53787, please only post a question once.