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5952 Discussions

Some trouble with HDMI RX ip core (Bitec IP core)

Altera_Forum
Honored Contributor II
924 Views

hi,guys  

I have some trouble when I used HDMI 2.0 IP CORE on my own Arroa 10 board.  

Nvidia GTX1060 is used HDMI 2.0 test signal source, connect to FPGA serdes pin through my own connect board. I can see pll is locked, and GXB is ready, and HDMI core is locked, but the trouble is vid_lock is always low.And HDMI RX core have aux_data, audio_data output but have no vedio_data(vid_data,vid_de,vid_h,vid_v) output. 

But when I loopback TX&&RX, RX CORE can output all vedio_data successful,which tx is sent color bar generated by myself using HDMI_TX IP CORE . 

 

Any idea what this could be? Thanks for any help!
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7 Replies
Altera_Forum
Honored Contributor II
127 Views

Updata : I am confused whether have no HDCP KEY will cause this problem.

Altera_Forum
Honored Contributor II
127 Views

doese the HDMI IP free?

Altera_Forum
Honored Contributor II
127 Views

 

--- Quote Start ---  

hi,guys  

I have some trouble when I used HDMI 2.0 IP CORE on my own Arroa 10 board.  

Nvidia GTX1060 is used HDMI 2.0 test signal source, connect to FPGA serdes pin through my own connect board. I can see pll is locked, and GXB is ready, and HDMI core is locked, but the trouble is vid_lock is always low.And HDMI RX core have aux_data, audio_data output but have no vedio_data(vid_data,vid_de,vid_h,vid_v) output. 

But when I loopback TX&&RX, RX CORE can output all vedio_data successful,which tx is sent color bar generated by myself using HDMI_TX IP CORE . 

 

Any idea what this could be? Thanks for any help! 

--- Quote End ---  

 

 

Hey Tiber, have you managed to solve this? I am at the same situation.. Exactly as you described, PLL locked GXB locked, core locked and sees parallel data coming from GXB. But vid_lock is low and nothing comes out from the vid_ interface..
Altera_Forum
Honored Contributor II
127 Views

The reference design has some errors provided by Altera .

Altera_Forum
Honored Contributor II
127 Views

 

--- Quote Start ---  

The reference design has some errors provided by Altera . 

--- Quote End ---  

 

In terms of which bit? If you could point me to a direction it would be very much appreciated!
Altera_Forum
Honored Contributor II
127 Views

 

--- Quote Start ---  

In terms of which bit? If you could point me to a direction it would be very much appreciated! 

--- Quote End ---  

Hi there, I am trying to use the ATX Plls on the HDMI reference design. I have re-compiled the software to use the ATX configuration, however the TX PLLs are not getting locked.Any suggestions/information on this front?
Altera_Forum
Honored Contributor II
127 Views

 

--- Quote Start ---  

Hi there, I am trying to use the ATX Plls on the HDMI reference design. I have re-compiled the software to use the ATX configuration, however the TX PLLs are not getting locked.Any suggestions/information on this front? 

--- Quote End ---  

In case this may be useful to someone. I can post more details on request: 

[list] 

[*]It is not advisable to use ATX Plls for lower HDMI rates, this due to jitter performance restrictions of the ATX. 

[*]The NIOS sw that comes with the reference design has got two cases, for fPLL and ATX-PLLs, however the case for the ATX has a bug: The re-calibration process does not distinguish fPLL/ATX cases, however the re-calibration process for each is slightly different.Hope it helps 

[/list]
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