FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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6162 Discussions

Instantiating problem when simulating vip test pattern generator



I'm trying to simulate video processing ip, I do not vip license yet. Anyway, as I understand, it should be able to be simulated even without vip license.


I build a simple qsys system with test pattern generator ip, which includes just a clock, and I then generate a wrapper as the top module of the system. Then I synthesized the system, write testbench, and set the testbench file and launch simulating (modelsim_altera).

Then I see the following errors:

 Loading tpg_test.tpg_test_alt_vip_cl_tpg_0

Error: (vsim-3033) D:/project/FPM/video_test_prj/tpg_test/synthesis/submodules/tpg_test_alt_vip_cl_tpg_0.v(71): Instantiation of 'alt_vip_video_output_bridge' failed. The design unit was not found.

vsim-3033) D:/project/FPM/video_test_prj/tpg_test/synthesis/submodules/tpg_test_alt_vip_cl_tpg_0_scheduler.sv(75): Instantiation of 'alt_vip_tpg_multi_scheduler' failed. The design unit was not found.

Error: (vsim-3033) D:/project/FPM/video_test_prj/tpg_test/synthesis/submodules/tpg_test_alt_vip_cl_tpg_0.v(122): Instantiation of 'alt_vip_tpg_bars_alg_core' failed. The design unit was not found.


I'm wondering what could be wrong. I use the same simulation flow to simulate pll and my other design, it works fine. But when I simulate ip from vip suite, none of them can be loaded by modelsim_altera.


Can anybody help me with this? I attach my design(quartus prime standard 18.1) here.

Thank you very much in advance!




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2 Replies



The Video processing IP suite is protected with OpenCore Plus. The files generated by Platform Designer in the "synthesis" directory will be encrypted files and your simulation flow is probably incorrect. Platform designer can generate a simulation model for you and these are the files you should be using.


In the platform designer GUI, check the Menu-item Generate > Generate HDL.... > Simulation


Note that it's also possible to do a simulation with a gate-level netlist produced after synthesis and perhaps this is what you are aiming for here (?) but I believe this is not possible with OpenCore Plus if you do not have the full licence.


Kind regards



Thank you very much for the answer.

You are right, my simulation flow is not working for this case. I figured out to use to source msim_setup.tcl generated by the tool, the loading problem was solved.


With best wishes