Integrating Altera's FFT IP Core into Nios System

[Altera_Forum]

Hi all 

 I am new here and i have a problem with integrating Altera's FFT IP Core into a NIOS II System. I am using Quartus 7.1 and also Megacore IP 7.1.  I already have made a simple NIOS System with CPU, on-chip memory, uart jtag and timer. Now i want to integrate the FFT IP Core. My first problem is that i cannot make a correct component of the FFT in SOPC Builder. I have already made a version of the FFT Core through the use of the MegaWizard Plug-in Manager. So far so good. Now when i specifiy to make a new component in SOPC Builder in the component editer and choose the verilog file of the FFT it shows me all the signal (sink and source signals of the Avalon ST interface and also clk, reset). Now all the signals get assigned to global signals as interface. And the interface itself is empty. When i add a new interface i cannot choose to make a Avalon ST interface. Only Slave, Master, Custom Intstruction and Tristate. But no matter what i choose it always gets deleted after i finish the component. By clicking on add i get a empty list for the signals and the component won't get added to my NIOS system. Can anybody tell me how to make a component which is using the Avalon ST interface ? Every tutorial i found so far is about dealing with components using the Avalon MM interface.  The second problem is how to connect the FFT to the NIOS CPU. The NIOS CPU is of course using the Avalon MM interface so i have to make a "conversion" to the Avalon ST Interface. I found that you can use FIFO's and specifiy each input and output to be either MM or ST. So that should work. But i am wondering if there is a better way to do this ? For example using those Avalon ST Sink and Source components from the Debug and Performance Peripherals. Sadly i haven't found any documentation about those two components and what they actually really are doing.  Thanks for reading and any help.  Flo

[Altera_Forum]

Hello 

 Just in case anybody has also the same problem: I wrote to the support of Altera and they told me that the component builder in Quartus 7.1 doesn't support Avalon ST interfaces. So i upgraded to 7.2 and everything works fine. Was a very easy solution after all.  Flo

[Altera_Forum]

dear mr, thank you for your really interesting post, iam having really the same problem as you do, and i dont know how can i connect the FFT IP core and the Viterbi IP core, can you please tell me howa could you manage to solve this problem, i will be very glad if you help me in this :)

[Altera_Forum]

First i don't know the Viterbi IP Core. In my case where i had to connect the FFT to the NIOS CPU the main problem was to make a conversion from Avalon ST to MM interface as the FFT uses the ST interface both on input and output and the NIOS CPU uses the MM interface so you cannot directly connect them. 

Anyway the best way to connect the FFT is through the use of Scatter-Gather DMA's. Not only do they the interface conversion for you, they even free up the CPU because the task of delivering the input data to the FFT and the results from the FFT is done by those DMA's (you need 2, one for the connection from NIOS CPU to FFT and another one for the other way).  Hope this helps and good luck  Flo

[Altera_Forum]

thank you very much for your reply :) , but please can you kindly send me just an example to what have you done, can you send me the sopc builder project as an attachment to my mail alhassan_fattin@yahoo.com, i will be very glad if you helped me as my graduation project delivery is after one month only and i cant pass this problem :(

[Altera_Forum]

Sorry but i cannot do this. There are two reasons. First i don't have access anymore to the project as i already graduated from university. Second the project is property of the university and i couldn't send it to anybody, even if i still had access. 

Really it's not that hard, just read the documentation for the SGDMA's. I think there is also a Altera example somewhere where SGDMA's are used so you should get the idea how to implement them.  Flo

[Altera_Forum]

thank you really very much :) , i will try to read the documentation again and try find this example :) , thanks for your help :)

[Altera_Forum]

Sorry can i ask another question :o , when i call the SGDMA it makes only one Avalon Streaming bus, and when i call the FFT IP Core form the "Creat New Component" tool in the SOPC there are alot of streaming signals(around 20 signals) (clock,reset,source_sop,sink_sop,etc..... ) howa can i connect all these signals in the FFT block to the SGDMA ?