How does the EMIF IP translate the ALVMM address to the row/column/bank address required by DDR4? I took a thorough look at the External Memory Interfaces Intel Arria 10 FPGA IP User Guide (UG-20115), but I did not see anything regarding this.
Background: I am currently using Intel's EMIF IP to drive DDR4 memory, and I need to write a module to test the DDR4 interface. Knowing the address translation would be beneficial to how I implement this test.
The DDR4 memory device is 256Mb x16. The AVLMM address width is set to 25 bits.
