Intel P-tile HIP clock not visible during timing analysis "all clock report"

[Adithiya_R]

 Hi Everyone,  

      We are trying to run ptile pcie in end_point mode + user_logic, but during timing analysis "coreclkout_hip" the one generated by HIP ( hard pcie_ip core) and fed to user_logic , is not visible in the "all clocks report" 

what would be the procedure to enable this?

In Gen 3 1x8 256 bit with 250 Mhz mode, Quartus is not able to automatically detect this "coreclkout_hip" and do the timing analysis of user_logic that's synchronous with respect to this clock

[ShengN_Intel]

Hi,

May i know you generate the design example with pio?

Thanks,

Regards,

Sheng

[Adithiya_R]

Hi Sheng 

• We generate the intel Ptile ip with our custom logic instead of PIO, and these are the following ports, which are given below 

  rx/tx_pma_parllel_clk, ref_clk these are the only list getting visible, coreclkout_hip which is supposed to be 350 Mhz (gen4) or 250 Mhz(gen3) is not in the list

• Requirement : To perform timing analysis with respect to coreclkouthip or the corresponding port in custom logic (user_clk)

[ShengN_Intel]

Hi,

Please make sure the output clock coreclkout_hip being used internally like feeding to other logic. Make sure there's fanout or usage internally. May I know possible provide the design for taking a look?

Thanks,

Regards,

Sheng

[Adithiya_R]

It is directly connected to user_app, user_clk port. But not identified as clock by Quartus.

[ShengN_Intel]

Hi,

Have you properly output the user logic? I'm adfraid it's being optimized away.

Could you set Netlist Optimization Never Allowed to that user logic module?

Thanks,

Regards,

Sheng

[Adithiya_R]

Hi 

    PLD_CLOCK_FREQ will eventually reflect as coreclkout_hip, is it  ?

   if this is the setting , then user_logic ( bar_access fails ) ---- So suspecting this freq_change is causing some issues , for which we need timing_analysis wrt coreclkout_hip or user_clk 

And sof is working perfect for Gen3 and not working for gen4 where PLD_CLK_FREQ is the only change. why is that ?

[RongYuan]

Hi,

I'm helping the PCIe part.

PLD_CLOCK_FREQ will eventually reflect as coreclkout_hip, is it ?

--Yes

And sof is working perfect for Gen3 and not working for gen4 where PLD_CLK_FREQ is the only change. why is that ?

--Probably the user logic part is not able to run correctly at 350MHz.

Regards,

Rong

[Adithiya_R]

Hi,

    Yes, our user logic is unstable at 350 MHz.

    To figure this out we need to enable the Timing analysis with respect to Coreclkout_hip

    That clock is not seen in the timing analysis. How to enable that?

[RongYuan]

Testing a PCIe Gen4 1x8 350MHz PIO design in Q25.1 Pro, the coreclkout_hip can be seen at the pio side as below screenshot. You may find similar clock input for your user logic.

Another two 350MHz clocks from dut|dut|inst|Inst|maib_and_tile are from a pcie wrapper file already constrained in pcie sdc files.

Regards,

Rong