Interacting with HPC II DDR3 Controller via Avalon-pipeline bridge
When we try to access the HPC II controller with own Avalon-MM Master through Avalon-MM pipeline bridge,the slave doesn’t response as expected during sequential read issues.Controller can accept read requests over or under maximum pending read transaction count.Actually maximum pending read transaction count doesn’t effect number of pending read transaction that is accepted by slave.The slave accepts constant read transaction request regardless of Avalon-MM Bridge’s maximum pending read transaction count parameter.(we keep asserted the amm-read and update amm-address when see the amm-waitrequest deasserted.With fixed amm-burstcount.)
Altera reccommends over-estimate the maximum pending read transaction count when use Avalon-MM pipeline bridge but under-estimating or over-estimating this parameter doesn’t effect the slave behavior. Could you inform me about this subject?