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Altera_Forum
Honored Contributor I
2,659 Views

Interfacing Avalon On-Chip Memory Core to a custom Avalon MM Master

Hello, 

 

I am trying to implement a custom Avalon MM Master to write into an On-Chip memory. This memory will later be accessed by a PCIe megafunction. My input is a data stream from a camera. As such, I thought there is no use in implementing a waitrequest signal, as the camera will not wait with supplying new data. However, the Avalon MM Master interface requires a waitrequest signal to be implemented("... all Avalon-MM master ports compulsorily support variable wait-states."), and throws errors when I don't do so and try to connect it to the memory(Error: memory.onchip_memory2_0.s1: Master avalon_master_1_1_1_1 does not have a waitrequest signal. Slave must match master's read and write wait time (read:1 write:1) ). The s1 latency here was 1 cycle on the memory. 

 

The thought process would be to have the memory used as a kind of FIFO-like circular frame buffer by circulating addresses, where the data is written in the memory by frames, the memory stores multiple frames, and the PCIe megafuction reads the frame put in 1-2 frames before the current frame(so the read and write never points to the same place). As such, the interrupt signal would be sent after every frame to the megafunction, and it would free up much of the CPU. 

 

I thought of using the Avalon ST Streaming interface for this, but that can't access the memory addresses as I would like to.  

 

Could anyone advise me what to do in this situation?
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12 Replies
Altera_Forum
Honored Contributor I
98 Views

You could have the waitrequest signal, and assign it to zero within your module. This way "Error: memory.onchip_memory2_0.s1: Master avalon_master_1_1_1_1 does not have a waitrequest signal. Slave must match master's read and write wait time (read:1 write:1)" will not be an issue and your functionality will not change.

Altera_Forum
Honored Contributor I
98 Views

Thank you for your answer, I have since then come up with another solution. 

 

The problem has been also modified a bit, but as of now I would approach the problem like this: In most cases if you are transferring some data to a memory, you are not happy if some data gets lost in the process.  

 

Thus for these cases, ignoring the waitrequest signal, as you suggested is not a good idea(though it is a solution for the exact problem). The solution for this is to implement a FIFO between the memory and the signal source in such a way, that the read from the FIFO is stalled when the waitrequest is asserted from the memory. If there are large enough pauses between the data writes to the FIFO( in the camera example, blanking) then a single clock FIFO can be used; otherwise a dual clock FIFO with a faster clock on the memory side should be used. 

This can be implemented using the Avalon MM interface, but as the Avalon MM FIFO is slave from both sides, you have to implement the writing and reading logic to and from the FIFO yourself. 

 

I hope this will be helpful for someone :)
Altera_Forum
Honored Contributor I
98 Views

Hi, how to access the on-chip memory core from a custom avalon mm master? where can I find such sample for reference? Thanks.

Altera_Forum
Honored Contributor I
98 Views

Add a RAM from the IP Catalog in Platform Designer (Qsys).

Altera_Forum
Honored Contributor I
98 Views

Sorry, What does you mean? On-chip memory does acts as RAM.

Altera_Forum
Honored Contributor I
98 Views

Oh you've already added it to your system. Them just connect it to your master and set a base address to access it.

Altera_Forum
Honored Contributor I
98 Views

There had been a master in my ip and have the on-chip memory connected to it, now the on-chip memory slave has two connection, one connects to the master of Pcie core ip and my self-defined ip. The on-chip memory had been mapped to address 0x02000000 in pcie core master, how and what address should the on-chip memory map to my ip? I am very confused about this.

Altera_Forum
Honored Contributor I
98 Views

It can be at the same address or a different one for your master. Check the Address Map tab to set the addresses.

Altera_Forum
Honored Contributor I
98 Views

The address both are 0x02000000, but all I read through my master was ZERO. Do you have a sample for reference?

Altera_Forum
Honored Contributor I
98 Views

It's a memory. You have to write to it first before you can read anything. I guess I don't understand what you are trying to do or what the issue is.

Altera_Forum
Honored Contributor I
98 Views

Thanks, I know this. And finally I found the problem, I used the Avalon MM Master template, but I gave it a reset_n for RESET signal, so it was always in reset state, that results in all ZERO.

Altera_Forum
Honored Contributor I
98 Views

Hi, I still have the problem when using Avalon MM Master template. It is ok to read data from a on-chip memory that connected on Avalon bus when the reading address is less than 0x1000, when above 0x1000 all the data read from on-chip memory is ZERO. The content of the on-chip memory had been initialized to no-zero value.

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