FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5982 Discussions

startix V hard ip pcie pld_clk_inuse is low

Honored Contributor II

Good afternoon colleague. 

Still trying to start hard ip core pcie. I figured out that the signal pld_clk_inuse is in a low state (0) and reset_status is in constan 1. 

Maybe someone had such an experience, where to start looking for a problem? 

Thank you in advance.
0 Kudos
0 Replies