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Altera_Forum
Honored Contributor I
782 Views

Why my self-defined QSys component does not have the same speed as on-chip memory ?

I am having a PCIe project based on QSys that have on-chip memory component and my self-defined component and a PCIe IP core connected on Avalon bus. I just want to check out what speed between PC program to the self-defined component can reach. 

https://alteraforum.com/forum/attachment.php?attachmentid=15375&stc=1  

 

Please see the attached photo, the first the avalon mm slave interface definition in my component, the second is the logic return the data to avalon mm master. 

https://alteraforum.com/forum/attachment.php?attachmentid=15376&stc=1  

 

As you can see I have implemented the burst read support, but there is no much improvement after adding burst read support. 

 

The speed of the on-chip memory component is about 2Gbps without using DMA, but my self-defined component has only about 130Mbps. 

 

My question is, 

 

1. How can I make a self-defined component has almost the same speed as on-chip memory component, is there a sample for reference? 

2. How can I access the on-chip memory from my self-defined component? 

 

Thank you!
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3 Replies
Altera_Forum
Honored Contributor I
32 Views

Adding bursting doesn't make your IP faster, you should only add it if you need it. That code you attached doesn't look like it's going to achieve what you are looking for. You have sections in the always block that are modifying the register "bc" so if that value is decrementing for each beat of the burst and getting reloaded by the next read at the same time you will most likely have a functional failure. Instead of spending time explaining how to structure this code I suspect your IP doesn't really need to support bursting since what you appear to be trying to code looks like a counter.

Altera_Forum
Honored Contributor I
32 Views

Thank you very much for you reply. 

 

That code is not the final version, it is used only for checking out the maximum speed can this ip reach, the register "bc" must have problem, but I think it should be OK for testing now. Actually I don't really need burst, what I want is to make my ip can be fast as on-chip memory ip, and the counter is only for test too, I just want to PC program can receive some data to verify the ip is working. Following is the code, can you help me to modify it to make it fast? Thank you. 

 

reg [31:0] mydata; 

reg [7:0] bc, bc1, bc2, bc3, bc4; 

 

always @(posedge clock) 

begin 

if (!resetn) 

begin 

mydata <= 0; 

avalon_readdatavalid <= 1'b0; 

end 

else 

begin 

if (avalon_read) 

begin 

bc <= avalon_burstcount; 

end 

else 

begin 

//avalon_readdatavalid <= 1'b0; 

end 

 

if (bc > 32'h0) 

begin 

mydata <= mydata + 1; 

avalon_readdatavalid <= 1'b1; 

 

bc <= bc - 1; 

end 

else 

avalon_readdatavalid <= 1'b0; 

end 

end
Altera_Forum
Honored Contributor I
32 Views

 

--- Quote Start ---  

Adding bursting doesn't make your IP faster, you should only add it if you need it. That code you attached doesn't look like it's going to achieve what you are looking for. You have sections in the always block that are modifying the register "bc" so if that value is decrementing for each beat of the burst and getting reloaded by the next read at the same time you will most likely have a functional failure. Instead of spending time explaining how to structure this code I suspect your IP doesn't really need to support bursting since what you appear to be trying to code looks like a counter. 

--- Quote End ---  

 

 

Thank you very much for your reply. 

 

The code is not the final version, it only be used to check what the maximum speed can this ip reach, so the register "bc" must have some problem, as well as the counter that returns to PC program that used only to verify the ip is working. 

 

Actually I don't really need bursting, what I want is to make a ip has the same speed as on-chip memory, can you give me some advise? Thank you.
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