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Altera_Forum
Honored Contributor I
723 Views

Interfacing TSE with Broadcom Gig-E Switch via RGMII

Hi All, 

 

I have been assigned the task of interfacing the TSE with a Broadcom 53115 Gig-E Switch via RGMII. I know that the register interface is SPI and that there are roughly 5000 registers in the device, accessed in a page-register/offset type of transfer; I've re-written the SPI access functions to perform write and reads correctly and am now in the process of wading through the TSE driver (largely altera_avalon_tse.c) and changing facets of it to work with a switch rather than a phy. 

 

For example, in this application, the tse is always set up as a gigabit link, the other 4 ports connected to the chip may or may not be, however the nios does not need to manage the autonegotiation/line rate advertisement, as this is handled by the switch. Simply setting up the i/o port to function in RGMII mode should be enough time for the outbound ports to establish a link. The function of establishing line rates connected to the 4 outbound ports (for reference purposes only) should be a matter of a few register accesses... 

 

I'm planning on documenting this little adventure here - was wondering if anyone on the forum has performed a similar task on the "canned" drivers? I planned on keeping the data structures as similar to the original implementation as possible to cut down on integration pains... love to hear input on this... 

crayner
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2 Replies
Altera_Forum
Honored Contributor I
41 Views

Good stuff crayner, 

 

How do you plan to deal with the custom tags on the RGMII port? Also, having some experience with Broadcom, I'm not sure they'd be happy with a discussion on this topic "in the wild" :-) 

 

Best Regards, 

 

--slacker
Altera_Forum
Honored Contributor I
41 Views

Hi Slacker - 

Clearing Bit 0 of the Broadcom Header Control Register (page 0x02, address 0x03) disables the additional header info/tags (this is between the SA and the type/length field) to the attached ports.  

 

I was, however, planning on using the RGMII port as strictly a LAN port (no IMP) as my application does not need net management (or most of the other functions in the chip). First step has been just getting SPI traffic running...  

-C
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