Interfacing the DSP IP cores with Nios ii processor using Avalon-ST

[yt_liu]

I have successfully built a microphone signal filter using the CIC and FIR DSP IP cores, and now I want to store the output of the FIR filter to a Nios ii processor's main memory. I'm doing this in order to further read the output from multiple microphones from the main memory and then send them using the triple speed Ethernet IP. To do this, I tried to use the SGDMA IP core in Stream to Memory mode, which is supposed to store data from an Avalon-ST source to memory. However, the Avalon-ST interface of the FIR core's output and the SGDMA IP core's input are not compatible. The bits_per_symbol parameter for the FIR core varies with its output data width and cannot be set manually, while the bits_per_symbol parameter for the SGDMA core is fixed to 8. In addition, the SGDMA core requires packet transmission while the FIR core does not support that. The output width of my FIR filter is 16 bits and I want to change its output format to: 8 bits per symbol, 2 symbols per beat, and with packet support. Is there a convenient way to achieve my goal so that I can make the two Avalon-ST interface compatible? I am using Quartus Prime Standard 19.1 and I develop the system on an Arria V FPGA. Thanks.

[CheePin_C_Intel]

Hi,

As I understand it, you are trying to interface between the FIR IP and the SDGMA core directly. Sorry as I am not aware of direct way for this. Probably you might need to look into storing the FIR output into some memory and then create some logic to convert it into SDGMA compatible format. 

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[yt_liu]

Hi Chee Pin, your understanding is exactly correct! Thanks for the information. Do you have any suggestions on what memory IP core I should use in order to both store the data from the FIR IP to it and provide a Avalon-MM interface (I guess?) for the SGDMA module? Thanks.

[CheePin_C_Intel · Accepted solution]

Hi,

Thanks for your update. Sorry as I am not really a design expert and could not really comment on the right memory IP to use. However, depending on the size of memory required, you can explore into normal FIFO, on-chip memory ie ROM/RAM and also DDR IP. Note that you would still need to create some glue logic to perform the conversion on your own.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin 

[CheePin_C_Intel]

It is recommended for your to try to create simple test design and run through functional Modelsim simulation before you proceed to hardware test to help ruling out functional related issue.

[CheePin_C_Intel]

I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.