Internal Oscillator specs in Cyclone V and other Intel FPGA devices

[IDeyn]

Hi all!

I'm currently involved in project there we need to exploit internal oscillator IP. The target device we use is Cyclone V E. 

We faced a problem that during some little changing in code, which is not clocked by internal oscillator, we received an erroneous performance of a piece of code clocked by internal oscillator, which is likely the timing problem evidence. 

For now we decided to write create_clock constraint, but we don't know which parameter to put after set_clock_uncertainty command for the internal oscillator.

For that we need to know internal oscillator specs, but all that we know is its frequency - 100 MHz. 

So the questions are.

1. What are the specs of internal oscillator, in particular in Cyclone V devices?
2. What should we put after set_clock_uncertainty command, or we do not need to write that command for some reason?
3. Do we need to opt out Optimize Hold Timing for the part of the code clocked by the Internal Oscillator?
4. What is the reason for not to post specs of Internal Oscillator for now? Maybe to force users to use rarely to prevent possible problems?

[SreekumarR_G_Intel]

usually internal oscillator prone to more error compare to external one, But i dont have exact number as of now

Answer to your questions as below

I agree with you , i am not finding the internal oscillator specification either in the datasheet .Let me try to ask internal team and come back to you for the same

ii) I found constraints for max 10 devices , can you apply for the cyclone V and let me know how it go :)

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...

iii) Do we need to opt out Optimize Hold Timing for the part of the code clocked by the Internal Oscillator?

let see the internal oscillator tolerance and we can think about hold timing next.

iv) What is the reason for not to post specs of Internal Oscillator for now? Maybe to force users to use rarely to prevent possible problems?

iam not sure i know the answer for this question;

Thank you,

Regards,

Sree

[IDeyn]

Hi Sree!

Thank you very much for your answer. I'll wait for an update.

[SreekumarR_G_Intel]

Hello there ,

I believe the spec is very same as As Configuration DCLK , Table 61 for the 100 MHz (Max) ..(i.e min 42.6 and max is 100 Mhz).

Still i didnt get any update ..will let you know if I get some update.

Thank you,

Regards,

Sree

[IDeyn]

Hi Sree!

Thank you for your answer, I'll wait.

By the way, if it is so, and frequency can wander from 42.6 to 100 Mhz, it's a wrong way to put into constraints file create_clock command with -period 100 MHz setting.

--

Best regards,

Ivan

[SreekumarR_G_Intel]

Hello Ivan. Can I close the case for now and we can watch mode and see if possible to add more detail for the internal oscillator .

Thank you ,

Regards,

Sree