I'm actually using SDRAM Controller Core for my project at 110Mhz to drive the SDRAM chip. The user Guide UG-01085 specify PC100 for this IP.
Is that ok tu use it at 110Mhz? And upgrade at 135Mhz after this?
If you refer to attached screenshot from UG-01085 FIgure 96, I can see there are 2 clk in the pic.
I presume you are referring to "SDRAM clock" connected to the SDRAM chip ?
Since this is clock used by the SDRAM chip and not by FPGA, I suggest you to check up the SDRAM datasheet to find out about the supported clock tolerance info or perhaps you can also consult the SDRAM chip vendor directly.