FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

Is it a bug?

Honored Contributor II



We have been using the Altera Checksum block for offloading the TCP Checksum and all appears to function well in 99.9% of packets. However, it would appear that when the checksum should be 0xFEFF. It is always returned as 0xFFFF indicating the result before the final invert is 0. 


I hacked the code on the Nios side to detect a zero case and automatically make it a 1 to reflect what appears to be the missing final fold if it has grown beyond a 16bit number. This fixed the issue, and as a result we changed the Verilog to match a different algorithm. 


Have we used this block incorrectly and it was just luck it normally works or have we found a legitimate bug? 



0 Kudos
1 Reply
Honored Contributor II

I recommend dumping the packet to a file so that it can be reproduced without any of the networking. If it still fails then I would open a service request.