I used the Verilog code below:
module Memory( input we, clk, input [5:0] waddr, raddr, // address width = 6 input [3:0] be, // 4 bytes per word input [31:0] wdata, // byte width = 8, 4 bytes per word output reg [31:0] q // byte width = 8, 4 bytes per word ); // use a multi-dimensional packed array //to model individual bytes within the word (* ramstyle = "MLAB, no_rw_check" *) logic [3:0][7:0] ram[0:63];// # words = 1 << address width always_ff@(posedge clk) begin if(we) begin if(be) ram[waddr] <= wdata[7:0]; if(be) ram[waddr] <= wdata[15:8]; if(be) ram[waddr] <= wdata[23:16]; if(be) ram[waddr] <= wdata[31:24]; end q <= ram[raddr]; end endmodule
=> In the fit report I found that fitter used Logic LABs resources not MLABs, and as you can see in the Verilog I added ramstyle attribute with MLAB parameter.
How can I make fitter use MLAB resources in this case?
What you can do is right click the .vhdl -> insert template.
From there, look for the byte enable template and use it.
Usually, due to different coding style, it would be hard for the Quartus to determined the code to be infer. Let's us know if you still failed to infer after this.
I tried the solution above and added the ramstyle attribute to force MLAB utilization:
attribute ramstyle : string; attribute ramstyle of ram : signal is "MLAB, no_rw_check";
After compiling I found that fitter used logic LABs resources not MLABs as desired.
Is there any other solution?