Is there any way to initialize onchip-ram with auto-generated data instead of an .mif

[Altera_Forum]

Hello every one 

I have some puzzle in using altsyncram module, and I need your help! In my design, I want to initialize a altsyncram in a parameterized module. The data filling to ram should be generated with the parameter passed to this parameterized module. But it seems that altsyncram can only be initialized by a .mif file. How can I reach my purpose?  The another way to workaround it is to use verilog to declare a ram register array by specifying 'ramstyle' property with "M-RAM", just like the following code:  (* ramstyle = "M-RAM" *) reg ram;  But the ram constructed by this way can only be accessed by one port. Dual port accessing code will cause synopsys to allocate double onchip ram blocks, and that should be avoid in my design.  I had tried to generate .mif file in the intial block of module, and it didn't work because quartus II didn't support the system function such as $fopen, $fprintf, etc...  So, could anyone tell me how to initialize altsyncram programmatically in verilog? Or anyway to generate .mif file programmatically through verilog by calling a script? Or How to generate a TRUE Dual-port ram without using IP core such as altsyncram etc?  Thanks very much!

[Altera_Forum]

Would readmemb or readmemh help? If you open a Verilog file in Quartus and go to Edit -> Insert Template -> Verilog -> Full Design, the rom and readmem examples might help.

[Altera_Forum]

Hi, 

Thanks very much for your replying. I had checked the system function you mentioned, and found that they seemed can only initialize rams declared by registers, for I hadn't found any example of initializing instance of altsyncram by readmemh. I'm not sure if I had lost any message or example, so I'll try your suggestion and post the result latter.  In other words, I'm trying to use ' dont_replicate ' attribute to workaround the duplication of resource by declaring RAM like this: (* romstyle = "M-RAM", dont_replicate *) reg rams; But the time consumed by analyze&synthesis seems too long, I don't know if it really works and feel it will go bad...  Is there any other way to implement a onchip-ram based dual-port RAM block?

[Altera_Forum]

Hi, Mr.Rysc. 

I'm back. After reading the reference document about function $readmemb and $readmemh, I found they still need a file generated out of quartus's synthesis process. So that didn't meet my requirement. And for my another test about using ' dont_replicate ' attribute, unfortunately, it didn't work nevertheless. But the problem is solved in another way. I picked the code referenced with ROM out and wrote a seperate dual-port ROM module , and instantiated it in the original module. After synthesis I found the onchip ram block consumed by module had been reduced. So I think the problem is caused by the too much functions in a single module, and maybe it puzzled the synthesis tool.