Issue with BSP Creation for Nios-V/m Using LPDDR4 on Agilex-5 (Quartus 24.1 & 24.3.1)

[fa_fpga_enthusiast]

Hello,

We are encountering an issue while creating a BSP for the Nios-V/m targeting Agilex-5 using LPDDR4 as the processor memory. We have attempted this using Quartus 24.1 and 24.3.1 but faced the same problem in both versions.

Setup Attempted:

• We connected the data and instruction interfaces of Nios-V/m to the External Memory Interfaces (EMIF) IP directly.
• We also tried routing them through the Address Span Extender Intel FPGA IP before connecting to the EMIF.
• In both cases, the memory interface is detected correctly under the "Vectors" section as the "Reset Agent" in the parameters editor of the Nios-V/m.

Issue:

When creating the BSP, we receive the following errors:

[Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry, .exceptions, .rodata, .rwdata, .text, .bss, .heap, .stack]"
[Error] CPU "intel_niosv_m" has no memories connected to its Avalon host(s)
[Error] CPU "intel_niosv_m" reset memory "emif_2b" has no matching memory region.

The instance name of the EMIF IP core in our design is "emif_2b". The last line of the message is different if we use "Address Span Extender Intel FPGA IP". Additionally, we cannot manually add the required memory regions in the BSP Link Script within the BSP Editor, as the "Memory Region" field remains empty when attempting to add a region.

Additional Observations:

• This issue did not occur with Nios-V/m on Agilex-7 using Quartus 23.4, where the Address Span Extender IP was correctly assigned for different memory regions in BSP. In this case, we were using a DDR4 Memory.
• The issue also does not occur when using On-Chip RAM as the processor memory.
• A possible difference is that in Quartus 23.4, the EMIF IP’s memory interface is "Avalon Memory Mapped Agent", whereas in Quartus 24.1 and 24.3.1, it is "AXI4 Subordinate".
• The type of Nios-V/m data and instruction buses is "AXI4Lite Manager" in both setups (Agilex-7 with Quartus 23.4 and Agilex-5 with Quartus 24.1/24.3.1).

Request for Assistance:

Could you provide the correct procedure for using LPDDR4 memory as the memory of Nios-V/m with the corresponding EMIF IP in Agilex-5 FPGAs?

At this moment, we are particularly interested in the correct setup for Quartus 24.1 with "External Memory Interfaces (EMIF) IP" which is no longer available in Quartus 24.3.1. However, we also tested "External Memory Interfaces (EMIF) IP - LPDDR4" in Quartus 24.3.1 with a similar outcome.

Thanks in advance for your help!

[JingyangTeh]

Hi

You could follow the flow of the link below:

https://www.intel.com/content/www/us/en/docs/programmable/726952/22-1-21-2-0/hardware-design-flow-15362.html

In Quartus there is no option to initialize the EMIF to run the Nios V solely from the EMIF.

You would need to set the reset vector to a flash device, eg QSPI Flash and a bootcopier will then copy the elf into the EMIF to start running your Nios application.

Regards

Jingyang, Teh

[fa_fpga_enthusiast]

Hello,

Thanks for the reply.

The main problem is that the Address Span Extender is not visible as the processor's memory.

We found a workaround to make the Address Span Extender visible as memory for the processor by following the procedure described in the thread below:

Link to Intel Community Thread

Although the solution was provided almost 10 years ago, it surprisingly remains unresolved in the latest Quartus version. We successfully tested a similar approach on an Agilex-7 FPGA, though that was some time ago.

Also, in Quartus 24.1, in the Nios V Processor parameter editor, we could not find the Exception Agent section under "Vectors". Do we need to follow a special process to enable it? We are using "Nios V/m Microcontroller Intel FPGA IP".

Current Issue: BSP Generation Error

Now, we are facing another issue when creating the BSP. In our main QSYS module, we have QSYS submodules, each containing a Triple Speed Ethernet (TSE) IP core. The control ports of these TSE cores are exported to the top-level QSYS module and connected to the Avalon-MM interface of the processor.

When generating the BSP in Quartus 24.1, we receive this error:
SEVERE: There is duplication of connected device name "eth_tse_sgmii_avalon_arbiter_av_slave".

"eth_tse_sgmii" is the name of the TSE IP core included in the QSYS submodules. We did not face this issue in Quartus 23.4 when using a similar system for Agilex-7. The processor in both cases is Nios-V.

Observations & Workarounds

• The issue does not occur when TSE IP cores are instantiated directly in the main QSYS module.
• The error only appears when TSE IP cores are inside QSYS submodules.
• If we disconnect all the QSYS submodules from the Avalon-MM interface except one, the issue does not occur.
• Since we use multiple instances of the submodules, placing all TSE IP cores directly in the main QSYS module is not an ideal solution.
• We also have Modular Scatter-Gather DMA IP cores inside our QSYS submodule, but we did not face a similar issue corresponding to their Avalon-MM interface.

Request for Help

Could you suggest a workaround or a proper solution to resolve this issue while keeping the TSE IP cores inside QSYS submodules?

Thanks in advance for your support.

Best regards.

[fa_fpga_enthusiast]

Hello,

The issue regarding BSP creation when the TSE IP cores are instantiated in QSYS subsystems was observed in Quartus 24.1. Additionally, we encountered other BSP-related issues when the TSE IP core was instantiated in the design. For example, the information provided in the system.h file of the generated BSP, corresponding to the TSE IP core, does not appear to be correct.

These issues do NOT occur when using Quartus 24.3.1. Therefore, they are already resolved by Intel in the latest released Quartus.

However, in both Quartus versions, when the BSP is valid, we consistently receive the following warning after BSP generation:

⚠ WARNING:
"Master 'expanded_master' of module 'address_span_extender' published by embeddedsw.configuration.affectsTransactionsOnMasters embedded software assignment on slave 'windowed_slave' doesn't exist."

Does this warning require special attention?

Following the instructions from the Intel community thread link provided in our earlier message, we removed the # character from the following lines in the "altera_address_span_extender_hw.tcl" file located at:
<install_dir>/ip/altera/merlin/altera_address_span_extender

set_interface_assignment windowed_slave embeddedsw.configuration.isMemoryDevice 1  
set_interface_assignment windowed_slave embeddedsw.configuration.affectsTransactionsOnMasters "expanded_master"  

Without updating "altera_address_span_extender_hw.tcl", we could not see the "address span extender" as the visible memory of the processor for generating the BSP.

Additionally, please note that we are using DDR memory as the main memory for the Nios-V processor, with the address span extender placed between the processor and the DDR controller. We already have a similar system working on an Agilex-7 FPGA, and we are now upgrading the design for Agilex-5.

We don't receive the same warning when we generate the BSP for the Agilex-7 FPGA using Quartus 23.4.

Best regards.

[JingyangTeh]

Hi

Apologies for the late response.

In my project I tried adding the Address span extender and did not see the warning mention when generating the BSP.

Could you try "Assign Base Address", "Assign Interrupt Number" and "Sync System Infos" to see if this warning is still there?

After the BSP generation, it will not auto detect the memory region. You would need to manually define the memory region.

Regards

Jingyang, Teh

[fa_fpga_enthusiast]

Hello,

Thank you for your response.

You might not be seeing the warning because the "altera_address_span_extender_hw.tcl" file was not modified as we previously explained. Without this modification (or a similar one), how can the Address Span Extender be recognized as visible memory for the processor when generating the BSP?

Even if we attempt to define the memory regions manually, we are unable to select the Address Span Extender when pressing the "Add" button—unless the mentioned TCL file is already modified.

Additionally, manually defining memory regions every time we generate the BSP is not an ideal solution. We expect the tool to handle this automatically.

Also, we tried "Assign Base Address", "Assign Interrupt Number," and "Sync System Infos", but the warning is still there.

A screenshot is attached showing where the warning appears.

We are using Quartus 24.3.1.

Looking forward to your thoughts.

Best regards.

[fa_fpga_enthusiast]

I am attaching a new screenshot since the quality of the previous one was low.

[JingyangTeh]

Hi

I think it could be the naming when you add in the memory device.

It should be the same device name as the IP name in the PD.

Please find the screenshot below:

Regards

Jingyang, Teh

[fa_fpga_enthusiast]

Hello,

We’ve noticed a key difference in how the memory device name appears when using the Address Span Extender IP core.
In our case, the memory device name includes the suffix _windowed_slave, like so:
address_span_extender_0_windowed_slave

This seems to be the main difference between our system and yours.

The critical warning appears in the "Problems" tab when we press the "Generate BSP" button.
Didn't you encounter the same issue?
Also, could you confirm if you're using Quartus version 24.3.1?

Typically, the Address Span Extender is placed between the processor and a larger memory that exceeds the processor's addressable range. However, in your system, we noticed the processor is connected directly to the memory and also via the Address Span Extender.

We tried different connections and topologies and always received the warning.

In summary, here are the key differences we observed:

1. The memory device name in our system is address_span_extender_0_windowed_slave, while in yours, it appears without the _windowed_slave suffix. Could you please let us know why we are seeing this difference?
2. When we press the "Generate BSP" button, we receive the warning that we already mentioned in the "Problems" tab.

Best regards.

[JingyangTeh]

Hi

Yes. I am using 24.3.1.

I have removed the on chip memory and only with the emif and was able to generate the BSP.

When you add in the memory device you would need to add in the same name as the name mentioned in the PD.

If you memory device name contains the suffix "_windowed_slave" you would need to add in the suffix, if not you do not need to add it in.

Regards

Jingyang, Teh

[fa_fpga_enthusiast]

Hello,

You're not seeing the "_windowed_slave" suffix because the "cntl" port of the Address Span Extender is not connected to the "data_manager" port of the processor. This connection is typically required to allow the processor to modify the Address Span Extender's settings if needed.

Also, you're not seeing a warning in the "Problems" tab because the altera_address_span_extender_hw.tcl file located at:
<install_dir>/ip/altera/merlin/altera_address_span_extender
was not modified as described in the following Intel forum post:
https://community.intel.com/t5/Programmable-Devices/NIOSII-using-the-FPGA-to-HPS-SDRAM-Bridge-via-Address-Span/td-p/150256

As previously mentioned, we need to remove the # character from the following lines to enable automatic detection of the memory device:

#set_interface_assignment windowed_slave embeddedsw.configuration.isMemoryDevice 1  
#set_interface_assignment windowed_slave embeddedsw.configuration.affectsTransactionsOnMasters "expanded_master"  

We have now reinserted the # character before the second line, and as a result, the warning no longer appears.

Please note that removing the # from both lines used to work fine with Agilex 7 FPGAs.

Thanks again for your help!
You can go ahead and close this ticket.
We’ll test the generated BSP for Agilex 5 soon, and if we encounter any issues, we’ll open a new ticket.

Best regards,

[JingyangTeh]

Hi

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh