Issue with CIC filter implementation using DSP builder.

[Altera_Forum]

Hi, 

 I'm implementing a 2 stage CIC decimation(/1000) filter using the DSP builder but not using the CIC block rather using adder and substractor to implement it. As per my calculation the CIC filter will act as an 500 Hz low pass filter and 32 bits are needed for full resolution. Two input signals which are sine waves of 250 KHz ( sampling time is taken to be 1 MHz) are first fed to a multiplier and the output of the multiplier is then fed as an input to an adder. I should be getting a dc voltage at the output where I'm getting my original signal back at the output. I'm attaching the screeshot of the .slx file. Can anyone please help me with this ?   Note : The clock block of the Altera Blockset is set to 20 ns and the Simulink sampling time is also specified to be 1 MHz.  Thanks, Swarnava Pramanik

[Altera_Forum]

so your input sampled is at 100MHz(as 250KHz sine*cos), thus mult output is also sine wave at 100MHz (not dc). 

your filter decimates by 1000 but where is that decimation?

[Altera_Forum]

Hi Kaz, 

 Thanks for your reply. I forgot to put the downsampler over there. I'm updating a new screenshot. I'm getting a dc at the output but with random spikes. I thought of using a PLL as a clock divider to be placed between the integrator and the comb section but it won't allow me to add PLL block. Please have a look at the attachments and kindly suggest something. Thanks a lot. Note: 1st subplot is the final output

[Altera_Forum]

your final output truncation is 31:0 => 11:0, why? try 31:20

[Altera_Forum]

There is no need for PLL, you just needed decimation. Your truncation must keep the MSBs. The spikes should not occur but check your saturation internally or as test reduce input range or just use sine wave without mult.

[Altera_Forum]

--- Quote Start ---  There is no need for PLL, you just needed decimation. Your truncation must keep the MSBs. The spikes should not occur but check your saturation internally or as test reduce input range or just use sine wave without mult.  --- Quote End ---    Hi Kaz,  I tested without the multiplier also and got similar result as with the multiplier. In the pipelined adder I have used pipelined stage to be 1 as I need to delayed the output of the adder and feed it to the other input of the adder. I think something is wrong with my design. This time is gave the sine input as 250 Hz without the multiplier so I should be expecting a sine wave of same frequency at the output but I got a dc with unusual spikes.

[Altera_Forum]

the picture shows overflow in your integrator2

[Altera_Forum]

--- Quote Start ---  the picture shows overflow in your integrator2  --- Quote End ---    Hi Kaz,  What should I need to do to prevent this overflow ? Do I need to increase the number of bits ? Can you please suggest a way to resolve this ?   Thanks, Swarnava Pramanik