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Hi,

I'm implementing a 2 stage CIC decimation(/1000) filter using the DSP builder but not using the CIC block rather using adder and substractor to implement it. As per my calculation the CIC filter will act as an 500 Hz low pass filter and 32 bits are needed for full resolution. Two input signals which are sine waves of 250 KHz ( sampling time is taken to be 1 MHz) are first fed to a multiplier and the output of the multiplier is then fed as an input to an adder. I should be getting a dc voltage at the output where I'm getting my original signal back at the output. I'm attaching the screeshot of the .slx file. Can anyone please help me with this ? Note : The clock block of the Altera Blockset is set to 20 ns and the Simulink sampling time is also specified to be 1 MHz. Thanks, Swarnava PramanikLink Copied

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so your input sampled is at 100MHz(as 250KHz sine*cos), thus mult output is also sine wave at 100MHz (not dc).

your filter decimates by 1000 but where is that decimation?- Mark as New
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Hi Kaz,

Thanks for your reply. I forgot to put the downsampler over there. I'm updating a new screenshot. I'm getting a dc at the output but with random spikes. I thought of using a PLL as a clock divider to be placed between the integrator and the comb section but it won't allow me to add PLL block. Please have a look at the attachments and kindly suggest something. Thanks a lot. Note: 1st subplot is the final output- Mark as New
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your final output truncation is 31:0 => 11:0, why? try 31:20

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the picture shows overflow in your integrator2

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