Issue with the address of Avalon MM BFM master.

[TNguy162]

Hi all,

I'm new to this.

I'm trying to build a simulation environment to test my system by using Avalon Memory Map BFM master.

I'm having an issue with the address which is outside of the range I assigned to my components in my design.

My system has 2 writable RAM IP and a mSGDMA. I assigned them with the address from 0x4_0000 to 0x4_8000 by using Platform designer. When I wrote a random data to the address 0x0000 then read back at the same address, the chip select of the RAM-which has address of 0x4_0000-is active. The RAM replied the correct data for the read command that I wrote to 0x0000. I don't understand why the interconnect translated the address of 0x0000 and activates the chip select to write data to this RAM, other addresses (in the range from 0x4_0000 to 0x4_8000) of other components are ok. Would you please suggest the reason and a solution to fix this issue?

I appreciate any suggestion.

Thank you.

Best Regards,

Trung

[sstrell]

This is the "default slave" feature of the interconnect. You're accessing an address location outside of the address map of the master, so by default, it accesses the first slave that is in the legal address range. You can choose a different default slave by enabling a hidden column by right-clicking in the System Contents tab.

What behavior are you expecting by accessing address location 0? If you're using the Avalon response signal, you can receive a response from the interconnect that you are accessing at out-of-range slave.

#iwork4intel

[TNguy162]

Hi sstrell,

Thanks for your comment.

This is the "default slave" feature of the interconnect. You're accessing an address location outside of the address map of the master, so by default, it accesses the first slave that is in the legal address range. You can choose a different default slave by enabling a hidden column by right-clicking in the System Contents tab.

Great, I got it.

What behavior are you expecting by accessing address location 0? If you're using the Avalon response signal, you can receive a response from the interconnect that you are accessing at out-of-range slave.

I expected that nothing will be responded since I accessed the out-of-range address. I didn't check the response signal.

By the way, then I tried to implement a mSGDMA at the address of 0x30000, I tried to access this address but there is nothing changed on the Avalon MM interface of this address. I checked this and I found that Quartus inserted interconnect automatically. It seems like I don't understand much about the behavior of interconnect. I found some information in the Platform Designer document. I will check this.

Thank you.

Best Regards,

Trung

[sstrell]

Check out these and related online trainings:

https://www.intel.com/content/www/us/en/programmable/support/training/course/oqsyscreate.html

https://www.intel.com/content/www/us/en/programmable/support/training/course/oqsysfinish.html

#iwork4intel

[TNguy162]

Great, I appreciate your help.